| 摘要 |
PURPOSE:To make it possible to read information with a large operation margin even when any element is used as the load of a memory cell, by providing a reference potential generating circuit that varies in reference potential similarly to variances of high and low potentials of the memory cell according to those variances. CONSTITUTION:Characteristics of transistors Q61 and Q62 are equalized in design, the current amplification factor is denoted as beta, and currents of constant current sources I61 and I62 are also equalized; and base-emitter forward voltage drops of transistors Q61 and Q62 are denoted as Vf, and that of the load as V=f(IH+IR). In this case, expression I shows the emitter potential of transistor Q61, and expression II the emitter potential of Q62. From expression III, reference potential VR is obtained which is voltage drop Vf, for example, lower than a value obtained by halving those emitter potentials at emitter follower E. Therefore, using this reference potential generating circuit makes it possible to avoid a decrease in operation margin due to the manufacture process. |
