| 摘要 |
PURPOSE:To make transfer possible without knowing the state of a transfer destination by enabling a processor to respond to both its own and slave processor addresses among processing addresses sent onto a common bus in synchronous and stand-by operation. CONSTITUTION:When transfer processing address ''0000'' is sent to processor 311 via bus 2a by a transfer request, matcher circuit 61b of its own processor address operates to open a gate, so that transfer will become possible. At this time, the condition between processors 311 and 312 changes so that processor 312 will serve as the main processor. Then when processor address ''0000'' is sent onto bus 2a, matcher circuit 62a of the opposite processor address to processor 312 operates to open gate 52, so that the transfer will start. |
