| 摘要 |
PURPOSE:To reduce the parasitic capacitance in an IC of a static induction transistor logic element (SITL) with a V-groove in a process easier than usual for improving the operation characteristic by self-aligning the p-type gate layer and the mesa layer for the drain. CONSTITUTION:On a p-type substrat having an n-type buried layer, an n-epitaxial layer is piled up, and p-type layers 51-54 are selectively formed, on which an n- epitaxial layer 32 is piled up. The layer 32 does not accumulate on oxide films 81- 84 on the p-type layer surface, and the p-type layers 51-54 diffuse slightly outward into the layer 32. The whole is covered with SiO2 film 85, which is selectively removed: it is left on mesa layers 321 and 322, and a space is left on the edge of the film 85 on the groove buttom. The whole except the mesa layers 321 and 322 is practically levelled by anisotropy etching, in order to newly form grooves 42 and 43. Then n<+> and p<+> diffusions are selectively provided, followed by wiring, and forming an injector 5, gate 50 and drain 6. A buried layer 2 is led from the groove 42 through an n<+>-layer 62 in order to form a source 60, and the groove 43 is provided with p<+> diffusion 55 for element isolation. The constitution permits fine processing to be easy, so that an SITL of small parasitic capacitance can be obtained. |
