| 摘要 |
In a data processing system central processor units (10 and 10A), input/ output units (12), memory units (11) and secondary storage units (24, 25, and 26, 27) are interconnected by a bus (14). When one of the units, for example the processor unit (10), is to transfer information to a second unit, for example the controller (20) of the memory units (11) over the bus (14), the first unit, to prevent other units gaining access to the bus, generates a first signal onto a line in the bus (14) for a predetermined number of clock pulses, e.g. one cycle conflicting requests for bus access being resolved by priority arrangements. The second unit then takes over generation of the first signal on the bus line after the predetermined number of clock pulses up to the end of the transfer. <IMAGE> |
