发明名称 PARITY CHECK METHOD AND ITS UNIT
摘要 PURPOSE:To make unnecessary the memory unit and signal lines for parity bit, by adding the parity bit immediately after the output instruction of one block and performing the parity check immediately before the execution of block output instruction. CONSTITUTION:The parity check register PCR is independently provided, and the operation of exclusive logical sum EOR between the instruction code and the code in the parity check register PCR is made before the execution of each instruction, and the result is again stored in the parity check register PCR. This operation is repeated in each instruction, and the parity bit is picked up before the execution of instruction and parity check is made at final output instruction.
申请公布号 JPS55105758(A) 申请公布日期 1980.08.13
申请号 JP19790012901 申请日期 1979.02.07
申请人 FUJI ELECTRIC CO LTD 发明人 ASANO HIDEJIROU;TOMIZAWA KEIICHI
分类号 G06F11/10 主分类号 G06F11/10
代理机构 代理人
主权项
地址