发明名称 PROGRAMMABLE SEQUENCE CONTROLLER
摘要 PURPOSE:To make it possible to constitute all sequence instruction including arithmetic instructions into one word by performing processes with microprogram muPG provided with instructions except mode instruction setting an arithmetic function, as to CPU on a muPG system. CONSTITUTION:This controller consists of input-output point 13 meeting an external apparatus, memory unit 12 stored with data and sequence instructions, and muPG system CPU11 executing sequence arithmetic, and each sequence instruction is composed of one word of instruction part 41 and operand part 42. Then, muPG is provided with mode instructions for setting arithmetic functions, operand setting instructions, operator setting instructions, and arithmetic-result storage instructions, and an object to be set by each instruction is the operand part. When the mode instruction is sent, operand part 42 is temproarily stored in CPU11 and the stored arithmetic function is executed on receiving the operator setting instruction. Consequently, various arithmetic operations become possible by one-ward constitution without increasing the number of bits of any one of sequence instruction parts.
申请公布号 JPS55962(A) 申请公布日期 1980.01.07
申请号 JP19780074511 申请日期 1978.06.20
申请人 TOKYO SHIBAURA ELECTRIC CO 发明人 SHIMOKAWA KATSUYUKI;HORIUCHI KIYOSHI
分类号 G06F7/00;G05B19/02;G05B19/05 主分类号 G06F7/00
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