| 摘要 |
A field-effect device, e.g. an insulated-gate field-effect transistor has field-relief means in the form of a polycrystalline silicon or other resistance layer connected between its gate and drain electrode to permit during operation of the device the formation of a potential distribution (VG, VD) along the resistance layer. The resistance layer and its potential distribution extend over the current path in a low-doped drain zone to permit a high drain breakdown voltage without an unacceptable increase in drain series resistance or unacceptable decrease in transconductance. |
