发明名称 |
Digital phase locked loop tuning system |
摘要 |
A phase locked loop circuit for use in an automatic frequency synthesizing system. The system includes a programmer circuit which is responsive to a channel number input signal and generates a first digital control signal which is representative of the selected channel number and a second digital control signal which is representative of a predetermined group of channel numbers. A programmable divider is controlled by the programming circuit and generates a digital output signal which causes the phase locked loop circuit to generate a desired system output frequency corresponding to the selected channel number input signal. The phase locked loop circuit includes automatic fine tuning and manual fine tuning features.
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申请公布号 |
US4121162(A) |
申请公布日期 |
1978.10.17 |
申请号 |
US19760695875 |
申请日期 |
1976.06.14 |
申请人 |
MOTOROLA, INC. |
发明人 |
ALBERKRACK, JADE HENRY;HILLIKER, STEPHEN EARL |
分类号 |
H03J5/02;H03J7/06;H03L7/193;(IPC1-7):H04B1/16 |
主分类号 |
H03J5/02 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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