| 摘要 |
A PLL circuit, a recording apparatus, and a clock signal generating method are provided to reduce a phase error of the PLL circuit due to amplitude variation of an input signal. A PLL(Phase Locked Loop) circuit(100) includes a VCO(110), a A/D converter(120), a normalizer(130), a divider(140), a phase comparator(150) and, an LF(Loop Filter)(160). The VCO changes an oscillation frequency of a clock signal according to the signal inputted from the phase comparator through the LF. The A/D converter converts a wobble signal that is the analog input signal by using the clock signal which the VCO oscillates as the sampling clock and outputs the converted signal to the normalizer. The normalizer receives the digital signal which the A/D converter digitizes and normalizes the amplitude value of the digital signal. The normalizer outputs the normalized digital signal to the phase comparator. The divider receives the clock signal which the VCO oscillates and divides the signal into n. The divider feeds back the n divided signal as a comparison clock signal to the phase comparator. The phase comparator controls the phase of the clock signal which the VCO outputs in order to equalize the phase of the normalized digital signal of the normalizer with the phase of the fed back n divided comparison clock signal of the divider.
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