| 摘要 |
Input frames TAR, TARB of each of two diversity digital channels, shifted randomly in time, are applied to respective variable delay memories, which in turn provide in-phase frames on the selection terminals of an output switch. An error masking circuit, including an error detector having various levels of error gravity, and a priority encoder for comparing errors between the two channels and an R-S flip-flop, is connected between each input terminal and a switch control terminal. The better quality frame of the two digital channels is selected and provided as the output signal of the dynamic switching circuitry.
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