| 发明名称 |
A toggle flip-flop with a reduced integration area |
| 摘要 |
A toggle flip-flop (FFT) with reduced integration area, comprising a flip-flop of the D type with an inverting input stage (T,A,B,C) and a master-slave portion. Three transistors (M1,M2,M3) connected to the inverting stage form a logic gate of the XOR type whereto the output terminal (Q) of the master-slave portion is fed back. <IMAGE>
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| 申请公布号 |
EP0899878(A1) |
申请公布日期 |
1999.03.03 |
| 申请号 |
EP19970830432 |
申请日期 |
1997.08.29 |
| 申请人 |
STMICROELECTRONICS S.R.L. |
发明人 |
ROSSI, ANNAMARIA;FUCILI, GIONA;CANE, MARCELLO;NESSI, MAURIZIO |
| 分类号 |
H03K3/037;H03K3/356;(IPC1-7):H03K3/00 |
主分类号 |
H03K3/037 |
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