| 摘要 |
PROBLEM TO BE SOLVED: To realize a memory of which operation speed is fast, a process cost is inexpensive, in which external refresh-operation is not required, and which is easy to use in the case of plural access. SOLUTION: This device is provided with a first circuit RFPDRAM comprising plural memory cells and operated based on a first clock signal CLK1, a second circuit A and a third circuit B coupled to the first circuit RFPDRAM, and a bus BUS for coupling the first circuit RFPDRAM, the second circuit A, and the third circuit B, the second circuit A outputs a first address signal to the first circuit RFPDRAM based on the second clock signal CLK2, the third circuit B outputs a second address signal to the first circuit RFPDRAM based on the third clock signal CLK3, the first circuit RFPDRAM comprises a refresh-control circuit performing refresh-operation of plural memory cells based on a fourth clock signal CLK4 and an address buffer taking in the first or the second address signal based on the first clock signal CKL1, and a frequency of the first clock signal CLK1 is sum of frequency of the second, the third, and the fourth signals CLK2-CLK4 or more. |
