INSTRUCTION AND LOGIC FOR REGISTER BASED HARDWARE MEMORY RENAMING

摘要

A processor includes a core, a memory subsystem, a predictor module, and a memory rename module. The predictor module may include a first logic to identify a dependency between a store instruction and a load instruction, and a second logic to assign a memory renaming (MRN) register to the store instruction and the load instruction based on the identified dependency. Further, the memory rename module may include a third logic to copy, based on the assigned MRN register, information in a first logical register associated with the store instruction directly to a second logical register associated with the load instruction.

主权项

1. A processor, comprising:
a core; a memory subsystem; a predictor module including:
a first logic to identify a dependency between a store instruction and a load instruction for execution by the core; anda second logic to assign a memory renaming (MRN) register to the store instruction and the load instruction based on the identified dependency; and a memory rename module including a third logic to copy, based on the assigned MRN register, information in a first logical register associated with the store instruction directly to a second logical register associated with the load instruction.