| 摘要 |
A data transmission system including a slave device ( 30 ) and a master device ( 10 ) is disclosed. Slave device ( 30 ) may include a slave side clock signal generator section ( 32 ) for generating a slave side clock signal (CLKSOUT), a phase adjusting circuit ( 40 ) for controlling a phase of a slave side clock signal (CLKSOUT), output sections ( 33 - 1 to 33 -m) for outputting transmission data signals (SD 1 to SDm) in response to slave side clock signal (CLKSOUT), and a timing reference signal generator section ( 34 ) for outputting a timing reference signal (SSPH) in response to slave side clock signal (CLKSOUT). Master device ( 10 ) may include a master side clock signal generator section ( 11 ) for generating master side clock signal (CLKM), input sections ( 12 - 1 to 12 -m) for sampling data signals (SD 1 to SDm) in response to master side clock signal (CLKM), and a phase compare circuit ( 19 ) for generating a phase adjustment instruction signal (SADJOUT) based upon timing reference signal (SSPH) and master side clock signal (CLKM). Phase adjusting circuit ( 40 ) may adjust a phase of slave side clock signal (CLKSOUT) in response to phase adjustment instruction signal (SADJOUT). In this way, data setup and/or hold times may be improved.
|
