| 摘要 |
A receiver path including first, second, third, and fourth comparator modules. The first comparator module is configured to generate, based on a signal received via the receiver path, a first digital output signal indicative of a sum of first data in the received signal and a first error. The second comparator module is configured to generate, based on the signal received via the receiver path, a second digital output signal indicative of a sum of second data in the received signal and a second error. The third comparator module is configured to generate, based on the signal received via the receiver path, a third digital output signal indicative of the first data in the received signal. The fourth comparator module is configured to generate, based on the signal received via the receiver path, a fourth digital output signal indicative of the second data in the received signal. |
| 主权项 |
1. A receiver path for processing a received signal including first data and second data, the receiver path comprising:
a first comparator module configured to (i) receive only the first data in the received signal and (ii) generate, based on a first clock signal, a first digital output signal, wherein the first digital output signal is indicative of a sum of the first data in the received signal and a first error associated with the first comparator module, and wherein the first data and the first error correspond to odd data and an odd error, respectively; a second comparator module configured to (i) receive only the second data in the received signal and (ii) generate, based on a second clock signal, a second digital output signal, wherein the second digital output signal is indicative of a sum of the second data in the received signal and a second error associated with the second comparator module, and wherein the second data and the second error correspond to even data and an even error, respectively; a third comparator module configured to (i) receive only the first data in the received signal and (ii) generate, based on the first clock signal, a third digital output signal, wherein the third digital output signal is indicative of the first data in the received signal; and a fourth comparator module configured to (i) receive only the second data in the received signal and (ii) generate, based on the second clock signal, a fourth digital output signal, wherein the fourth digital output signal is indicative of the second data in the received signal. |
