Nonvolatile semiconductor memory and method of manufacturing the same

摘要

A trench region 14 is formed in a memory cell P-type well 13. Two NAND-type memory cell units ND1 and ND2 are respectively formed along both side wall portions of this trench region 14. A floating gate FG and a control gate CG in these NAND-type memory cell units ND1 and ND2 are formed self-aligningly without using a photoresist. One bit line BL connected to the two NAND-type memory cell units ND1 and ND2 is formed via an interlayer dielectric 30. The bit line pitch of this bit line BL is set at 2 F. Hence, the size of a nonvolatile semiconductor memory can be reduced.