Instructions and functions for evaluating program defined conditions

摘要

A compare instruction of an instruction set architecture (ISA), when executed tests one or more operands for an instruction defined condition. The result of the test is stored as an operand, with leading zeros, in a general register of the ISA. The general register is identified (explicitly or implicitly) by the compare instruction. Thus, the result of the test can be manipulated by standard register operations of the computer system. In a superscalar processor, no special “condition code” renaming is required, as the standard register renaming takes care of out-of-order processing of the conditions.

主权项

1. A computer implemented method comprising:
executing, by a processor, one or more instructions to set a condition code in a condition code register to be tested by a branch-on-condition instruction; executing, by the processor, a compare instruction specifying one or more general registers distinct from the condition code register, the executing comprising:
obtaining a first operand consisting of a number of bits;obtaining a second operand consisting of said number of bits;comparing, by the processor, the first operand and the second operand to determine a condition, the condition indicating a result of the comparing; andstoring, by the processor, the condition in one of said instruction specified general registers without overwriting the condition code register, said one of said instruction specified general registers storing said number of bits; and executing, by the processor, a branch-on-condition instruction that tests the condition code of the condition code register to determine whether a branch is taken or not-taken.