Delay-locked loop circuit with fractional phase frequency detector

摘要

A delay-locked loop (DLL) has a fractional phase frequency (PF) detector that reduces false locking and harmonic locking. The PF detector has a trunk, an upper branch, a lower branch, and a logic module. A delay line provides the PF detector a set of fractional phase-delayed clock signals that are used to prime and/or activate corresponding flip-flops of the trunk, upper branch, and lower branch in a sequence. The use of flip-flops in the lower branch activated by different fractional phase-delayed clock signals avoids false locking and harmonic locking over a wider range of initial delay magnitudes than conventional DLLs.

主权项

1. A delay-locked loop (DLL) circuit that receives an input clock signal and generates an output clock signal having a desired phase delay relative to the input clock signal, the DLL circuit comprising:
a delay line that receives the input clock signal and a delay-line control signal and generates a plurality of fractional delay signals having different phase delays relative to the input clock signal whose magnitudes are based on the delay-line control signal; a phase frequency (PF) detector that receives the plurality of fractional delay signals from the delay line and generates UP and DOWN control signals based on the plurality of fractional delay signals; a charge pump that receives the UP and DOWN control signals and generates a pump current based on the UP and DOWN control signal; and a loop filter that receives the pump current and generates the delay-line control signal based on the pump current, wherein the PF detector comprises:
a trunk activated by a fractional delay signal of the plurality of fractional delay signals;an upper branch primed by the trunk and activated by a fractional delay signal of the plurality of fractional delay signals; anda lower branch primed by the trunk and comprising a serial chain of one or more data modules that are sequentially activated by one or more of the plurality of fractional delay signals, wherein the DLL converges to the desired phase delay over a range of initial phase delay magnitudes.