A gate array LSI having functional blocks formed by interconnecting a plurality of basic cells (10) arranged on a semiconductor substrate in matrix form and either signal conductive patterns (7) or first power conductive patterns (5). The first power conductive patterns (5) are disposed on the plurality of basic cells (10) arranged in line and are divided and disposed on the basic cells so that the signal conductive pattern (7) is interposed therebetween. It is therefore possible to improve the efficiency of wiring macrocells. <IMAGE>
