发明名称 Method to manufacture a split gate P+ EEPROM memory cell
摘要 A method of forming a split gate EEPROM memory cell which has exclusively a thermally-grown oxide separating a side of a floating gate from an opposing side of a control gate, and separating the control gate from the underlying substrate. The method includes the steps of forming a doped polysilicon floating gate over a first portion of a channel, forming an oxide-nitride-oxide (ONO) dielectric over the doped polysilicon floating gate, oxidizing a side of the doped polysilicon floating gate to form a thermally-grown silicon dioxide (SiO2) dielectric, and forming a control gate over a second portion of the channel, wherein the thermally-grown silicon dioxide (SiO2) dielectric is interposed between the floating gate and the control gate. An alternative implementation of a method adds another silicon nitride layer on top of the ONO dielectric to protect the underlying oxide from a cleaning process.
申请公布号 US2002168818(A1) 申请公布日期 2002.11.14
申请号 US20010855477 申请日期 2001.05.14
申请人 BERGEMONT ALBERT 发明人 BERGEMONT ALBERT
分类号 H01L21/28;H01L21/336;H01L29/423;H01L29/51;H01L29/788;(IPC1-7):H01L21/336 主分类号 H01L21/28
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