SEMICONDUCTOR DEVICE

摘要

A trench gate type MOS gate structure is provided in an active region on a substrate front surface side, and a floating p-type region is provided in a mesa region between trenches. A groove is provided distanced from the trench in a surface layer on the substrate front surface side of the floating p-type region. A second gate electrode is provided across an insulation layer in the interior portion of the groove. The second gate electrode covers the surface on the substrate front surface side of the floating p-type region. Thus, the second gate electrode is embedded in a surface layer on the substrate front surface side of the floating p-type region between the floating p-type region and an interlayer dielectric, whereby the substrate front surface is flattened. Controllability of turn-on di/dt is high, mirror capacitance is low, and an element structure having an intricate pattern can be formed.

主权项

1. A semiconductor device, comprising:
a first semiconductor layer of a first-conductivity-type; a second semiconductor layer of a second-conductivity-type selectively provided in one surface layer of the first semiconductor layer; a third semiconductor layer of the first-conductivity-type selectively provided in an interior portion of the second semiconductor layer; a trench that has inner walls and an interior portion, and that penetrates the second semiconductor layer and the third semiconductor layer to reach the first semiconductor layer; a fourth semiconductor layer of the second-conductivity-type selectively provided in one surface layer of the first semiconductor layer and isolated from the second semiconductor layer by the trench; an interlayer dielectric that covers the fourth semiconductor layer; a fifth semiconductor layer of the second-conductivity-type provided in another surface layer of the first semiconductor layer; a first electrode conductively connected to the second semiconductor layer and the third semiconductor layer and electrically isolated from the fourth semiconductor layer by the interlayer dielectric; a second electrode conductively connected to the fifth semiconductor layer; a gate insulating film provided along an inner wall of the trench within the interior portion of the trench; a first gate electrode provided on an inner side of the gate insulating film within the interior portion of the trench; a groove that is provided, distanced from the trench, on the interlayer dielectric side of the fourth semiconductor layer and that has inner walls and an interior portion; an insulation layer provided along an inner wall of the groove within the interior portion of the groove and covering the fourth semiconductor layer; and a second gate electrode provided on an inner side of the insulation layer within the interior portion of the groove and covering the insulation layer.