| 发明名称 | Time-interleaved skew reduced pipelined analog to digital converter | ||
| 摘要 | A system includes a first storage element to store an input signal for a first sampling lane for a SHA-less stage. A first switch is connected with the first storage element, the first switch to control when the first storage element stores the input signal for sampling on the first sampling lane. A second switch is connected in series with the first switch, the second switch to control an instance for sampling the input signal stored on the first storage element for the first sampling lane. | ||
| 申请公布号 | US8878707(B1) | 申请公布日期 | 2014.11.04 |
| 申请号 | US201313967819 | 申请日期 | 2013.08.15 |
| 申请人 | Broadcom Corporation | 发明人 | Wang Tao;Chen Chun-Ying;Brandolini Massimo;Chou Wei-Te |
| 分类号 | H03M1/00;H03M1/12 | 主分类号 | H03M1/00 |
| 代理机构 | Brinks Gilson & Lione | 代理人 | Brinks Gilson & Lione |
| 主权项 | 1. A system, comprising: a first storage element to store an input signal for a first sampling lane for a SHA-less stage; a first switch connected with the first storage element, the first switch to control when the first storage element stores the input signal for sampling on the first sampling lane; and a second switch connected in series with the first switch, the second switch to control an instance for sampling the input signal stored on the first storage element for the first sampling lane. | ||
| 地址 | Irvine CA US | ||