| 摘要 |
PURPOSE:To obtain a frequency sweep signal which is free from the variation of amplitude up to 1/2 sampling frequency, by deciding the sweep coefficient of the frequency sweep signal so that the sampling point of a signal of 1/2 sampling frequency (fs) is coincident with the peak point of the amplitude of the sampled signal. CONSTITUTION:This circuit is actuated by a clock (frequency fs) supplied from a terminal 11 as well as the reset signal supplied to a terminal 10. A constant pi/4n produced by a constant generating circuit 1 is supplied to a circuit which consists of a coefficient circuit 9, an adder circuit 2, a register 3 and an adder circuit 4 and produces (2i+1). The output of the circuit 4 is added with the output (showing the present phase phii) of a register 6 through an adder circuit to calculate the next clock phase phii+1. The phase phi1 is used as an input to perform the conversion of data through a fixed memory 7, and the obtained data Z(ti) is converted again into an analog signal through a D/A conversion circuit 8. Thus a desired frequency sweep signal can be obtained at a terminal 12. |
