SCAN DRIVING CIRCUIT

摘要

A scan driving circuit is disclosed for executing a driving operation for cascaded scan lines and includes a pull-down control module, a pull-down module, a reset control module, a reset module, a down-stream module, a first bootstrap capacitor, a constant low-level voltage source utilized, and a constant high-level voltage source. The whole structure of the disclosed scan driving circuit is simple, and power consumption is low.

主权项

1. A scan driving circuit, utilized for executing a driving operation for cascaded scan lines, comprising:
a pull-down control module utilized for receiving a previous-stage scan signal and generating a low-level scan signal corresponding one of the scan lines according to the previous-stage scan signal; a pull-down module utilized for pulling down a scan signal of the corresponding scan line according to the low-level scan signal; a reset control module utilized for receiving a next-stage clock signal and generating a reset signal of the corresponding scan line according to the next-stage clock signal; a reset module utilized for pulling up the scan signal of the corresponding scan line according to the reset signal; a down-stream module utilized for generating and transmitting a present-stage clock signal and a present-stage pull-down control signal according to the scan signal of the scan line; a first bootstrap capacitor utilized for generating a high level or a low level of the scan signal of the scan line; a constant low-level voltage source utilized for providing a low-level signal; and a constant high-level voltage source utilized for providing a high-level signal; wherein the scan driving circuit utilizes P-type metal-oxide-semiconductor field-effect transistors or N-type metal-oxide-semiconductor field-effect transistors to control the pull-down control module, the pull-down module, the reset control module, and the reset module; the pull-down control module further receives a next-stage scan signal and generates the low-level scan signal of the corresponding scan signal according to the next-stage scan signal; the reset control module further receives a previous-stage clock signal and generates the reset signal of the corresponding scan signal according to the previous-stage scan signal.