Digital phase locked loop.

摘要

An improved digital phase locked loop (DPLL) has a fixed bandwidth independent of manufacturing and environmental variations. The DPLL bandwidth is optimized by monitoring (20) the delay propagation, i.e., the "silicon speed", of the module. This information is used by a bandwidth regulator to control the characteristics of the low pass filter (14) in the phase locked loop. The digital phase locked loop is also programmable to allow the user to control the phase shifting of the retiming clock. A phase shift control for a second, slave controlled oscillator (24) is used to retime the received data. This phase shift control allows the user to control the phase shifting of a retiming latch (28). <IMAGE>