发明名称 METHOD FOR ANALYZING VALIDITY OF COMPUTER CACHE
摘要 PROBLEM TO BE SOLVED: To provide a system and method at low costs for deciding the effect of cache while continuously activating this system for long time in the actual software work load of a customer. SOLUTION: A computer bus 100 carries an address and a memory transaction including a transaction type. An address filter 102 selects the address by a prescribed algorithm, and allows only transaction data related with the address to a transaction capturing memory 104. When the memory is made full, a computer 106 reads the captured transaction from a transaction capturing memory 104. The address filter 102 selects the set of different addresses, and this process is repeated. The computer 106 applies the captured transaction to a software model 108 of cache. The computer 106 generates a statistical result 110 based on the result of the transaction in the modeled cache.
申请公布号 JP2000003294(A) 申请公布日期 2000.01.07
申请号 JP19990083446 申请日期 1999.03.26
申请人 HEWLETT PACKARD CO <HP> 发明人 BRIAN D GAISER;ROBERT B SMITH
分类号 G06F11/34;G06F12/08;(IPC1-7):G06F11/34 主分类号 G06F11/34
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