发明名称 FAILURE DIAGNOSTIC METHOD FOR LOGIC INTEGRATED CIRCUIT
摘要 PROBLEM TO BE SOLVED: To reduce a data storage amount required for a failure analysis, by a method wherein a logic output expected-value pattern in replaced with a defect logic output pattern, and failure detection results in the execution of failure simulations are compared. SOLUTION: A logic input pattern 1 and a logic output expected-value pattern 2 are inputted, a failure simulation 5A is executed, and an expected-value failure detection result 6 is obtained. On the other hand, the logic output expected-value pattern 2 is replaced with a defect logic output pattern 4 from a defect logic integrated circuit 10, a failure simulation 5B is executed, and a defect failure detection result 7 is obtained. Then, a comparison means 8 compares the expected-value detection result 6 with the defect failure detection result 7, and it points out a failure-place candidate point on the basis of result data from a disagreement node 9. As a result, the creation of a failure dictionary in every failure simulation is omitted, and it is possible to eliminate enormous storage data for the failure dictionary.
申请公布号 JP2000046917(A) 申请公布日期 2000.02.18
申请号 JP19980216332 申请日期 1998.07.31
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 NISHI KIYOKAZU
分类号 G01R31/28;G06F11/26;(IPC1-7):G01R31/28 主分类号 G01R31/28
代理机构 代理人
主权项
地址