| 摘要 |
A device for phase alignment between a data signal and a main clock signal, characterized by the fact that, from a main clock signal, it has some means of generation of clock signals which are phase-shifted with respect to one another by a fraction of a period of said main clock signal, some means 10 of dividing the input data signal by sampling of said signal by said clock signals in order to obtain data signals with a length equal to said fraction of a period of said main clock signal, observation window 14 of said sampled data bits, said window 14 having a length equal to a data bit of the entering signal, a set of pipelines 16 for parallel processing using an algorithm of the signals transmitted by the observation window in view of retrieving data signals, and device 18, 19 for drift compensation.
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