| 摘要 |
PURPOSE:To enable the read-in and write-in even at refresh cycle, by detecting the agreement with the refresh address and the designated address and accessing the dynamic memory with the designated address. CONSTITUTION:At refresh cycle, the output of the refresh address counter RFAC is fed to the dynamic memory MEM via the multiplexer MPX1 controlled with the control circuit CNTL as the row address for refresh. In this case, when the read-in address is set to the address register ADRR2 from the input control unit IOC, the row address and the content of the counter RFAC are fed to the comparison circuit MAT and if they are in agreement, the agreement signal is fed to the circuit CNTL. Then, the address set to the register ADRR2 accesses the memory MEM via the multiplexer MPX1 and the read-in by the designated address is made. This is the same for the write-in and read-in and write-in can be made during the refresh cycle. |
