| 摘要 |
<p>A phase-locked loop is supplied with a random two-level code sequence derived from a clock pulse having a frequency f0 to generate a local clock pulse which is in phase and frequency synchronization with the clock pulse. The local clock pulse is supplied by means of a voltage control oscillator controlled in accordance with a phase difference signal and a phase supplement signal. The phase difference signal is indicative of the difference in phase between an input signal and a discrimination signal. The phase supplement signal is derived by a signal generator responsive to the phase difference signal and the local clock pulses.</p> |
