| 发明名称 | High-voltage tolerant input voltage buffer circuit | ||
| 摘要 | Described is an apparatus comprising a first node to receive signal; a second node to provide an output signal; a voltage limiter circuit operating under a first supply voltage, the voltage limiter coupled to the first and the second nodes; and a bypass circuit operating under the first supply voltage, the bypass circuit coupled to the voltage limiter circuit and is capable of being enabled to electrically short the first node to the second node. | ||
| 申请公布号 | US9608636(B2) | 申请公布日期 | 2017.03.28 |
| 申请号 | US201314129238 | 申请日期 | 2013.09.24 |
| 申请人 | Intel Corporation | 发明人 | Lau Ker Yon |
| 分类号 | H03K19/0185;H03K19/003;H03K19/0175;H03K5/08;G06F1/26;H03K17/16 | 主分类号 | H03K19/0185 |
| 代理机构 | Blakely, Sokoloff, Taylor & Zafman LLP | 代理人 | Blakely, Sokoloff, Taylor & Zafman LLP |
| 主权项 | 1. An apparatus comprising: a first node to receive signal; a second node to provide an output signal; a voltage limiter circuit to operate under a first supply voltage, the voltage limiter circuit coupled to the first and second nodes; and a bypass circuit to operate under the first supply voltage, the bypass circuit coupled to the voltage limiter circuit, the bypass circuit capable of being enabled to electrically short the first node to the second node. | ||
| 地址 | Santa Clara CA US | ||