| 摘要 |
A direct memory access controller (DMAC) (10) which executes direct memory access (DMA) transfers is provided with: a check start address storage unit (300) which stores a check start address (301) indicating the position at which to start a check; a control unit (100) which determines whether a DMA transfer is being executed and, if it is determined that a DMA transfer is not being executed, outputs a read request (101A) for reading data from memory; a data reading unit (140) which, when a read request (101A) is output, reads check data (142A) that includes read data (132) starting from a position indicated by the check start address (301); and a determination unit (110A) which determines whether there is an error in the read data (132). |
