Solid state imaging device and electronic apparatus

摘要

Provided is a solid state imaging device including: a pixel portion where pixel sharing units are disposed in an array shape and where another one pixel transistor group excluding transfer transistors is shared by a plurality of photoelectric conversion portions; transfer wiring lines which are connected to the transfer gate electrodes of the transfer transistors of the pixel sharing unit and which are disposed to extend in a horizontal direction and to be in parallel in a vertical direction as seen from the top plane; and parallel wiring lines which are disposed to be adjacent to the necessary transfer wiring lines in the pixel sharing unit and which are disposed to be in parallel to the transfer wiring lines as seen from the top plane, wherein voltages which are used to suppress potential change of the transfer gate electrodes are supplied to the parallel wiring lines.

主权项

1. An imaging device, comprising:
a semiconductor substrate including a plurality of photoelectric conversion portions, wherein the plurality of photoelectric conversion portions are arranged to share at least a floating diffusion, a reset transistor electrically connected to the floating diffusion, and an amplification transistor electrically connected to the floating diffusion; a first transfer transistor electrically connected to a first photoelectric conversion portion of the plurality of photoelectric conversion portions; and a plurality of metal layers disposed at a side of the semiconductor substrate opposite a light-incident side of the semiconductor substrate, wherein the plurality of metal layers includes:
a first transfer wiring line electrically connected to a gate electrode of the first transfer transistor and disposed to extend in a horizontal direction;a reset wiring line electrically connected to a gate electrode of the reset transistor and disposed in parallel to the first transfer wiring line, wherein the reset wiring line is disposed in a same layer of the plurality of metal layers as the first transfer wiring line; anda metal wiring disposed between the first transfer wiring line and the reset wiring line in the same layer as the first transfer wiring line, wherein the metal wiring is configured to receive a fixed voltage.