SOLID STATE DISK CONTROLLER APPARATUS

摘要

A solid state disk controller apparatus comprises a first port; a second port having a plurality of channels; a central processing unit connected to a CPU bus; a buffer memory configured to store data to be transferred from the second port to the first port and from the first port to the second port; a buffer controller/arbiter block connected to the CPU bus and configured to control read and write operations of the buffer memory based on a control of the central processing unit; a first data transfer block connected between the first port and the buffer controller/arbiter block and configured to transfer data to be stored/read in/from the buffer memory bypassing the CPU bus; and a second data transfer block connected between the second port and the buffer controller/arbiter block and configured to transfer data to be stored/read in/from the buffer memory bypassing the CPU bus.

主权项

1. A solid state drive (SSD) comprising:
a plurality of nonvolatile memory devices; a buffer memory; a host interface circuit configured to interface signals including a command and data with an external host device; a central processing unit (CPU) configured to control a read operation and a write operation of the SSD in response to the command; a first buffer circuit configured to interface the data between the host interface circuit and the buffer memory; a flash interface circuit configured to control the plurality of nonvolatile memory devices under a control of the CPU; a plurality of channels connected between the flash interface circuit and the plurality of nonvolatile memory devices; a plurality of second buffer circuits configured to interface the data between the buffer memory and the flash interface circuit, the plurality of second buffer circuits corresponding to the plurality of nonvolatile memory devices, the plurality of second buffer circuits being configured to communicate with the plurality of nonvolatile memory devices via the flash interface circuit; and one or more error checking and correcting (ECC) circuits configured to detect and correct errors on the data transferred from the plurality of nonvolatile memory devices to the plurality of second buffer circuits, wherein each of the plurality of channels corresponds to respective one of the plurality of second buffer circuits, and at least two nonvolatile memory devices among the plurality of nonvolatile memory devices share a control signal.