Continuous diffusion configurable standard cell architecture

摘要

At least one configurable circuit cell with a continuous active region includes at least one center subcell, a first-side subcell, and a second-side subcell. Each center subcell includes first and second pMOS transistors and first and second nMOS transistors. The first pMOS transistor has a first-pMOS-transistor gate, source, and drain. The first-pMOS-transistor source is coupled to a first voltage source. The second pMOS transistor has a second-pMOS-transistor gate, source, and drain. The second-pMOS-transistor source is coupled to the first voltage source. The first-pMOS-transistor drain and the second-pMOS-transistor drain are a same drain. The first nMOS transistor has a first-nMOS-transistor gate, source, and drain. The first-nMOS-transistor source is coupled to a second voltage source. The second nMOS transistor has a second-nMOS-transistor gate, source, and drain. The second-nMOS-transistor source is coupled to the second voltage source. The first-nMOS-transistor drain and the second-nMOS-transistor drain are a same drain.

主权项

1. A semiconductor die comprising at least one configurable circuit cell comprising:
at least one center subcell, each of the at least one center subcell comprising:
a first p-type metal oxide semiconductor (pMOS) transistor having a first pMOS transistor gate, a first pMOS transistor source, and a first pMOS transistor drain, the first pMOS transistor source being coupled to a first voltage source;a second pMOS transistor having a second pMOS transistor gate, a second pMOS transistor source, and a second pMOS transistor drain, the second pMOS transistor source being coupled to the first voltage source, the first pMOS transistor drain and the second pMOS transistor drain being a same drain;a first n-type metal oxide semiconductor (nMOS) transistor having a first nMOS transistor gate, a first nMOS transistor source, and a first nMOS transistor drain, the first nMOS transistor source being coupled to a second voltage source; anda second nMOS transistor having a second nMOS transistor gate, a second nMOS transistor source, and a second nMOS transistor drain, the second nMOS transistor source being coupled to the second voltage source, the first nMOS transistor drain and the second nMOS transistor drain being a same drain; a first side subcell on a first side of the at least one center subcell; and a second side subcell on a second side of the at least one center subcell, the at least one center subcell, the first side subcell, and the second side subcell having a continuous active region.