| 摘要 |
According to an aspect of the present invention, provided is a delay locked loop circuit including: a plurality of delay cells that sequentially generate internal clock signals by using a reference clock signal and a delay control value; a phase detecting unit that compares an interval clock signal output from a final one of the plurality of delay cells with the reference clock signal and outputs an error adjusting signal; a delay control unit that generates a new delay control value by using the error adjusting signal and the delay control value to sequentially store the new delay control value, and calculates an average value of the stored delay control values; and a control signal output unit that calculates optimum delay control values for the delay cells by using the average value. The delay locked loop circuit and a digital pulse width modulation circuit according to the present invention can be stably driven without being influenced by a semiconductor manufacturing process, a supply voltage, and a temperature and can implement excellent performance with a simple structure and low costs. |
