发明名称 METHOD OF DECOMPOSING LAYOUT OF SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE USING THE SAME
摘要 In a method of decomposing a layout of a semiconductor device, a polygon, which includes a plurality of intersections at each of which at least two lines are crossed, among polygons included in the layout of the semiconductor device may be determined as a complex polygon. A first stitch may be inserted between the plurality of intersections on the complex polygon. A plurality of decomposed patterns may be generated by performing a pattern dividing operation on the layout.
申请公布号 US2016070838(A1) 申请公布日期 2016.03.10
申请号 US201514737244 申请日期 2015.06.11
申请人 KANG Dae-Kwon;JUNG Ji-young;KIM Dong-Gyun;YANG Jae-Seok;HWANG Sung-Wook 发明人 KANG Dae-Kwon;JUNG Ji-young;KIM Dong-Gyun;YANG Jae-Seok;HWANG Sung-Wook
分类号 G06F17/50;H01L21/311;H01L21/768 主分类号 G06F17/50
代理机构 代理人
主权项 1. A method of decomposing a layout of a semiconductor device, comprising: determining a polygon is a complex polygon among polygons included in the layout of the semiconductor device, the complex polygon including a plurality of intersections where at least two lines are crossed; inserting a first stitch between the plurality of intersections on the complex polygon; and generating a plurality of decomposed patterns by performing a pattern dividing operation on the layout.
地址 Yongin-si KR