An ESD device that includes a gate and an n-drain region isolated from the gate and formed at least partially within an n-well region, which in turn is formed at least partially within a deep n-well region. The doping levels of the n-drain region, the n-well region and the deep n-well region are in a descending order. The ESD device has trigger and holding voltages, above the operation voltage of its protected circuit, which are layout-configurable by altering the distance between the n-drain and a side edge of the n-well region.
申请公布号
WO2015109088(A3)
申请公布日期
2015.11.12
申请号
WO2015US11593
申请日期
2015.01.15
申请人
CYPRESS SEMICONDUCTOR CORPORATION
发明人
LEE, SUNGKWON;BETTMAN, ROGER;DHANRAJ, SAI PRASHANTH;HO, DUNG;LUQUETTE, LEO, F.;GATABI, IMAN REZANEZHAD;WALKER, ANDREW