Memory controller supporting concurrent volatile and nonvolatile memory modules in a memory bus architecture

摘要

A memory/storage module is provided that implements a solid state drive compatible with Serial Advanced Technology Attachment (SATA) or Serial Attached SCSI (SAS) signaling on a double-data-rate compatible socket. A detachable daughter card may be coupled to the memory module for converting a memory bus voltage to a second voltage for memory devices on the memory module. Additionally, a hybrid memory bus on a host system is provided that supports either DDR-compatible memory modules and/or SATA/SAS-compatible memory modules. In one example, the memory/storage module couples to a first bus (DDR3 compatible socket) to obtain voltage and/or other signals, but uses a second bus for data transfers. In another example, the memory module may repurpose/reuse electrical paths that typically carry non-data signals for data traffic to/from the memory/storage module. Such data traffic for the memory/storage module permits concurrent data traffic for other memory modules on the same memory bus.

主权项

1. A memory controller, comprising:
a first circuit adapted to perform read and write operations over a memory bus according to signaling of a first memory type, the memory bus including a plurality of electrical paths coupled to a plurality of sockets; a second circuit, different from the first circuit, adapted to perform read and write operations over the memory bus according to signaling of a second memory type, different from the first memory type; and a switch coupled to only a first socket of the plurality of sockets and to the first circuit and second circuit, the switch adapted to:
select an input from either the first circuit or second circuit depending on which type of memory module is coupled to the first socket, andoperationally couple the selected input to only the first socket, via a subset of the plurality electrical paths of the memory bus, wherein the subset includes at least two differential pairs for each of the plurality of sockets coupled to the memory bus, wherein the first and second circuits are adapted to concurrently communicate with memory modules of the first memory type and second memory type, respectively, via the memory bus, wherein communication between the first circuit and a memory module of the first type that is coupled to a second socket, different from the first socket, is unaffected by the selection made by the switch coupled to the first socket, and wherein:
if a memory module of the first memory type is detected on the first module socket, then the switch operationally couples one or more clock signals to the first socket, andif a memory module of the second memory type is detected on the first socket, then the switch operationally couples one or more data traffic signals to the first socket.