Time reference systems for CPU-based and optionally FPGA-based subsystems

摘要

A time reference system includes a master clock, generating a clock reference, interface logic and a CPU-based subsystem. The interface logic receives the clock reference and generates the clock, pulses, and timestamp signals. The CPU-based subsystem includes an internal counter, a CPU and a clock synthesizer, the CPU and receiving the pulses and timestamp signals. The clock synthesizer receives the clock signal and generates a CPU clock signal. Some examples include an FPGA-based subsystem having an FPGA-based card coupled to the interface logic for receipt of the clock, pulses and timestamp signals. In a method the timestamp value TO is generated by the CPU upon receipt of the timestamp signal. Upon receipt by the CPU of the next pulse signal, a timestamp counter baseline value TSCO is generated so the CPU internal counter is calibrated to the clock signal.

主权项

1. A time reference system comprising:
a master clock capable of generating a clock reference; interface logic coupled to the master clock for receipt of the clock reference, the interface logic capable of generating the following signals: clock, pulses, and timestamp signals; the clock signal being based on the clock reference, the pulse signal being a signal having a frequency substantially different than the clock signal, and the timestamp signal being a signal comprising the actual time of day corresponding to a chosen following pulse; and a CPU-based subsystem comprising:
a CPU coupled to the interface logic for receipt of the pulses and timestamp signals, the CPU comprising an internal counter;a clock synthesizer coupled to the interface logic for receipt of the clock signal, the clock synthesizer capable of generating a CPU clock signal, the CPU clock signal being a function of the clock signal; andthe CPU coupled to the clock synthesizer for receipt of the CPU clock signal for use by the internal counter.