发明名称 MULTIPLE COMPUTE NODES
摘要 An example apparatus comprises a first compute node including a first processor; a second compute node including a second processor; an input/output (I/O) interface to selectively couple the first and second compute nodes to a set of I/O resources; and a voltage regulator including a set of power phase circuits, the voltage regulator to operate in a fault tolerant mode to provide power from selected ones of a first portion of the set of power phase circuits to the first compute node and to provide power from selected ones of a second portion of the set of power phase circuits to the second compute node.
申请公布号 WO2015116096(A2) 申请公布日期 2015.08.06
申请号 WO2014US13816 申请日期 2014.01.30
申请人 HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. 发明人 KADRI, RACHID
分类号 G06F13/14 主分类号 G06F13/14
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