发明名称 Profiling and optimization of program code/application
摘要 A system and associated methods are disclosed for profiling the execution of program code by a processor. The processor provides an instruction set with special profiling instructions for efficiently determining the bounds and latency of memory operations for blocks of program code. Information gathered regarding the bounds and latency of memory operations are used to determine code optimizations, such as allocation of memory for data structures in memory more local to the processor.
申请公布号 US9063754(B2) 申请公布日期 2015.06.23
申请号 US201414209676 申请日期 2014.03.13
申请人 发明人 Felch Andrew C.
分类号 G06F9/44;G06F9/45;G06F9/24 主分类号 G06F9/44
代理机构 Wolf, Greenfield & Sacks, P.C. 代理人 Wolf, Greenfield & Sacks, P.C.
主权项 1. A system having a processor comprising: circuitry for implementing an instruction set of the processor; and circuitry for implementing a register file; wherein the register file provides operand inputs for instructions of the instruction set; wherein the instruction set comprises a profiling instruction that receives a first input and a second input from the register file and a third input either from the register file or from a special register whose value was set by a previous instruction; wherein the profiling instruction further causes the processor to: add a number of cycles required for a memory read operation to an accumulating value of the total amount of waiting that a given memory operation in the program code is responsible for incurring, wherein the number of cycles is either the actual number of cycles or the actual number of cycles minus one; andwherein the accumulating value is only added-to in the case that the memory read operation requires two or more cycles; wherein the profiling instruction is executed immediately after initiation of the memory operation instruction; and wherein the output to the register file that updates the accumulating value occurs during the waiting cycle in which the memory read data returns so as to not require an additional output to the register file during memory read operations that take only one cycle.
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