Circuit in dynamic random access memory devices

摘要

A circuit in dynamic random access memory devices includes a command extension circuit. The command extension circuit is configured to generate at least one multiple-cycle command signal by lengthening a single-cycle clock command signal from a command decoding circuit. Control logic extends and reduces the multiple-cycle command signal to provide additional functions such as burst length and burst chop. Additional control logic is configured to determine whether a clock signal is enabled in output control logic circuitry according to the multiple-cycle command and logic level generated in the output logic circuitry.

主权项

1. A circuit in dynamic random access memory devices, comprising:
a command extension circuit configured to generate at least one multiple-cycle command signal by lengthening a single-cycle command signal from a command decoding circuit;
wherein the command extension circuit further comprises:a first flip-flop coupled to the command decoding circuit, a second flip-flop and a first Or circuit, wherein the first flip-flop generates a first delay signal according to the single-cycle command signal from the command decoding circuit and sends the first delay signal to the second flip-flop and the first Or circuit; anda third flip-flop coupled to a second Or circuit, the second flip-flop and the first Or circuit, wherein the third flip-flop generates a third delay signal according to a second delay signal from the second flip-flop and a reset signal from a second Or circuit and sends the third delay signal to the first Or circuit;wherein the second delay signal is generated by the second flip-flop according to the first delay signal and the reset signal;wherein the reset signal is generated by the second Or circuit according to a burst length signal and an output signal of a second And circuit;wherein the output signal is generated by the second And circuit according to an A12 signal and a burst chop signal;wherein the first Or circuit is configured to generate the multiple-cycle command signal to a delay lock loop (DLL) circuit according to the first delay signal, the second delay signal, the third delay signal and the single-cycle command signal.