发明名称 |
MEMORY CONTROLLER, SEMICONDUCTOR DEVICE, SYSTEM BOARD, AND INFORMATION PROCESSING DEVICE |
摘要 |
<p>PROBLEM TO BE SOLVED: To shorten the time until a processor can read and write data from and to a memory while reducing power consumption.SOLUTION: When interruption to a processor occurs, a memory controller of an embodiment supplies a signal for causing a state, where at least either reading or writing data by the processor is allowed, to a memory to which a first clock is supplied. When a second clock is being supplied to the memory and after the memory is brought into a state where at least either reading or writing is allowed, the memory controller supplies the memory with at least either a signal for reading data or a signal for writing data by the processor. The second clock is generated by an oscillation circuit, which starts operating when the interruption to the processor occurs, and has a higher frequency than that of the first clock.</p> |
申请公布号 |
JP2015092372(A) |
申请公布日期 |
2015.05.14 |
申请号 |
JP20140253310 |
申请日期 |
2014.12.15 |
申请人 |
TOSHIBA CORP |
发明人 |
KANAI TATSUNORI;KIMURA TETSUO;FUJISAKI KOICHI;SEGAWA JUNICHI;SHIBATA AKIHIRO;TARUIE MASAYA;SHIRAI SATOSHI;SHIROTA YUSUKE;HARUKI HIROMI;TOYAMA HARUHIKO |
分类号 |
G06F12/00;G06F1/04;G06F1/32 |
主分类号 |
G06F12/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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