Optimized synchronous scan flip flop circuit

摘要

According to at least one exemplary embodiment, a synchronous active high reset scan flip flop is provided. The synchronous active high reset scan flip flop may include a data input, a serial input, a test enable input, a reset input, a clock input, a device output. It may also include an AND gate configured to receive the serial input and the test enable input and a multiplexer configured to receive the data input and a first output signal received from the AND gate. The multiplexer is operable in response to the reset input which is used to reset the flip flop in function mode, and permit scan test in test mode. The synchronous active high reset scan flip flop may also include a storage element configured to receive a second output signal received from the multiplexer and operable in response to a clock signal received from the clock input.

主权项

1. A synchronous active high reset scan flip flop comprising:
a data input; a serial input; a test enable input; a reset input; a clock input; a device output; an AND gate configured to receive the serial input and the test enable input, and output a first output signal; a multiplexer configured to receive the data input, the first output signal, and the reset input, and output a second output signal comprising one of the data input or the first output signal in response to the reset input being de-asserted or asserted, respectively, the reset input is used to reset the flip flop in a function mode, and permit scan test in a test mode; and a storage element configured to receive the second output signal, and output a device output upon receipt of an active edge of a clock signal.