发明名称 Memory system with sectional data lines
摘要 The system includes multiple sets of local data lines in one or more routing metal layers below the three-dimensional memory array and multiple sets of global data lines in one or more top metal layers above the three-dimensional memory array. Each set of one or more blocks include one set of the local data lines. Each bay includes one set of global data lines that connect to the group of sense amplifiers associated with the blocks of the respective bay. Each block includes a subset of first selection circuits for selectively coupling a subset of array lines of the first type to respective local data lines. Each block includes a subset of second selection circuits for selectively coupling a subset of the respective local data lines to global data lines associated with a respective bay.
申请公布号 US8982597(B2) 申请公布日期 2015.03.17
申请号 US201213362320 申请日期 2012.01.31
申请人 Sandisk 3D LLC 发明人 Yan Tianhong;Fasoli Luca
分类号 G11C5/02;G11C16/24;G11C13/00 主分类号 G11C5/02
代理机构 Vierra Magen Marcus LLP 代理人 Vierra Magen Marcus LLP
主权项 1. A data storage system, comprising: a memory array including a plurality of data storage elements; a plurality of signal lines positioned within the memory array including the plurality of data storage elements and in communication with the plurality of data storage elements; a plurality of local data lines outside the memory array including the plurality of data storage elements, different subsets of the local data lines are in selective communication with different subsets of the data storage elements via the signal lines; a plurality of global data lines outside of the memory array including the plurality of data storage elements and in selective communication with multiple subsets of the local data lines, the local data lines are positioned between the memory array including the plurality of data storage elements and a substrate for the data storage system; a first group of selection circuits connected to the signal lines and the local data lines to selectively electrically connect the signal lines to the local data lines; a second group of selection circuits connected to the subsets of local data lines and the global data lines to selectively electrically connect the subsets of local data lines to the global data lines; control circuitry connected to the global data lines; the local data lines are positioned in at least one metal layer below the memory array including the plurality of data storage elements and above the substrate which is below the memory array, the control circuitry connected to the global data lines, being positioned on the substrate; and the global data lines are positioned in at least one metal layer above the memory array including the plurality of data storage elements.
地址 Milpitas CA US