Identifying invalid cache data

摘要

Cache lines are identified that provide incorrect data for read requests. The cache lines are invalidated before the incorrect data causes processing failure conditions. The cache lines providing incorrect data may be detected according to a number of the same read requests to the same cache lines. The cache lines may also be identified according to an amount of time between the same read requests to the same cache lines. The same read requests to the same cache lines may be identified according to associated start addresses and address lengths.

主权项

1. An apparatus, comprising:
a memory configured to store data as cache lines; and logic circuitry configured to: characterize memory access requests of a plurality of memory access requests by;
a read start address; anda read length,wherein the logic circuitry is configured to increment a count value when a next memory access request to the cache line is characterized by a same read start address as the read start address and a same read length as the read length; identify potentially incorrect stored data in a cache line of the cache lines based on the characterized memory access requests of at least two memory access requests of the plurality of memory requests; and invalidate the potentially incorrect stored data in the cache line.