| 摘要 |
提供减低确定性抖动之锁频回路电路及搭载其的半导体积体电路。 FLL电路(112)系具有产生时脉的数位控制振荡器(140)，与产生控制时脉的振荡频率之频率控制码的FLL控制器(120)。FLL控制器(120)系具有使用第1及第2临限值，比较藉由数位控制振荡器(140)所产生之时脉的频率与幂乘之参照时脉的频率的频率比较部(121)，与以依据该比较结果，藉由数位控制振荡器(140)所产生之时脉的频率成为幂乘之参照时脉的频率之方式产生频率控制码的延迟码控制器(123)。数位控制振荡器(140)系藉由频率控制码，调整产生时脉的频率。; and an FLL controller that generates a frequency control code to control an oscillation frequency of the clock. The FLL controller includes: a frequency comparison unit that compares a frequency of a clock generated by the digital control oscillator with a frequency of a multiplied reference clock; and a delay code control unit that generates, based on a comparison result of the frequency comparison unit, the frequency control code so that the frequency of the clock generated by the digital control oscillator matches the frequency of the multiplied reference clock. The frequency comparison unit determines the frequency of the clock by using first and second thresholds. The delay code control unit generates the frequency control code according to a determination of the frequency comparison unit and outputs the frequency control code to the digital control oscillator. |
