发明名称 |
Block emulation techniques in integrated circuits |
摘要 |
Techniques for emulating a logic block in an integrated circuit (IC) design are provided. The techniques include identifying a plurality of logic elements that are connectable to formal logic block. These logic elements are connected to perform logic functions associated with the logic block. The logic block may be a physical logic block on one IC design and a non-existent logic block on another IC design. The logic elements and associated connections form an emulated logic block. |
申请公布号 |
US8954907(B1) |
申请公布日期 |
2015.02.10 |
申请号 |
US201313850244 |
申请日期 |
2013.03.25 |
申请人 |
Altera Corporation |
发明人 |
Hasran Syamsul Hani;Chan Ian Eu Meng;Ho Wai Loon;Heng Lee Shyuan;Loo Min Meng;Hamid Mohd Yusuf Abdul |
分类号 |
G06F17/50;G06F9/455 |
主分类号 |
G06F17/50 |
代理机构 |
Womble, Carlyle, Sandridge & Rice |
代理人 |
Womble, Carlyle, Sandridge & Rice |
主权项 |
1. A method of emulating a logic block in an integrated circuit (IC) design, comprising:
identifying a plurality of smaller logic elements that are connectable to emulate the logic block, wherein the logic block includes a one time programmable (OTP) block, and wherein the plurality of smaller logic elements cannot form a physical OTP block; flagging each of the plurality of smaller logic elements; connecting the plurality of logic elements to receive input signals and perform logic functions associated with the logic block converting the integrated circuit design from a first data structure relating to a first integrated circuit device to a second data structure relating to a second integrated circuit device; identifying that the logic block is needed in the integrated circuit design but does not exist in physical form among a plurality of logic elements available for the second integrated circuit device, wherein the plurality of smaller logic elements are included in the plurality of logic elements; and placing a boundary around the plurality of smaller logic elements to form an emulated logic block based on the logic block, wherein at least one method operation is executed through a processor. |
地址 |
San Jose CA US |