| 摘要 |
PROBLEM TO BE SOLVED: To solve the problem in which a configuration to add up outputs of a plurality of oscillators reduces a jitter component insufficiently.SOLUTION: An oscillation circuit of the invention has a plurality of phase-locked loops, a second phase comparator, an automatic delay circuit, an adder and a voltage divider. The phase-locked loops each include a first phase comparator for comparing phases of an input reference signal and a comparison signal, a loop filter for interrupting an unnecessary fluctuation in an output of the first phase comparator, and a voltage-controlled oscillation device (VCO) for adjusting an oscillation frequency on the basis of an output of the loop filter to generate a clock signal. The second phase comparator compares phases of outputs of the PLLs, and outputs a control signal for reducing a phase difference between the outputs. The automatic delayer delays the phase of the comparison signal on the basis of the control signal. The adder combines outputs from the second phase comparator. The voltage divider divides a voltage of an output from the adder. |
